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[Console] Memory.FIFO

Description: 操作系统中的 内存管理 FIFO算法模拟-OS FIFO memory management algorithm simulation
Platform: | Size: 1300 | Author: 静水 | Hits:

[Other resource] FIFO

Description: 一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows
Platform: | Size: 14894 | Author: wutailiang | Hits:

[CSharp] 页面置换算法（FIFO和LRU）

Description: 模拟操作系统虚拟存储中的页面置换算法采用FIFO算法和LRU算法-simulation operating system virtual memory pages the algorithm used FIFO replacement algorithm and LRU algorithm
Platform: | Size: 248832 | Author: 杨鼎新 | Hits:

[Data structs] FIFOandLRUarithmetic

Description: 最佳页面置换算法，FIFO，LRU的仿真。页面调用和置换过程有动态显示。内存分配页面数目和页面引用串的长度可以进行人工交互输入。 -best pages replacement algorithm, FIFO, the LRU simulation. Page calls and replacement process is dynamic display. Memory allocation of the number of pages and pages cited the length of string can be artificial interactive input.
Platform: | Size: 238592 | Author: 刘利辉 | Hits:

[Software Engineering] design-flow-speeding-up-dsp

Description: Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time.-Wavelets have been widely used in many sign al and image processing applications. In this p aper. a new serial-parallel architecture for wavele t-based image compression is introduced. It is based on a 4-tap wavelet transform. which is realized using some FIFO memory module 's implementing a pixel-level pipeline archite cture to compress and decompress images. The're al filter calculation over 4 blocks window is done using a tree of carry save adders to ensure t he high speed processing required for many appl ications. The details of implementing both com pressor decompressor and sub-systems are give n. The primarily analysis reveals that the prop osed architecture, VLSI implemented using current technologies, can process a video stream in real time.
Platform: | Size: 2837504 | Author: sdfafaf | Hits:

[VHDL-FPGA-Verilog] ug_fifo

Description: 可综合的FIFO存储器，全部在一个压缩包中，测试过，可以使用．-be integrated FIFO memory, all in a compressed package, tested, can be used.
Platform: | Size: 507904 | Author: 藏瑞 | Hits:

[Windows Develop] C++465134615

Description: 经典实例，用C++语言制作的the fifo method of memory distribute-classic example, C language fifo produced by the method of memory distribute
Platform: | Size: 92160 | Author: liyun | Hits:

[OS Develop] yemianguanli

Description: 题目：设计一个请求页式存储管理方案，并编写模拟程序实现 具体要求： 1、产生一个需要访问的指令地址流，为不失一般性，可以适当地（用人工指定地方法或用随机数产生器）生成这个序列，使得 50％的指令是顺序执行的。25％的指令均匀地散布在前地址部分，25％的地址是均匀地散布在后地址部分 2、 页面淘汰算法采用 FIFO页面淘汰算法，并且在淘汰一页时，只将该页在页表中抹去。而不再判断它是否被改写过，也不将它写回到辅存 3、产生一个需要访问的指令地址流；指定合适的页面尺寸（例如以1K或2K为1页；指定内存页表的最大长度，并对页表进行初始化 4、每访问一个地址时，首先要计算该地址所在的页的页号，然后查页表，判断该页是否在主存。如果该页已在主存，则打印页表情况；如果该页不在主存且页表未满，则调入一页并打印页表情况；如果该页不在主存且页表已满，则按 FIFO页面淘汰算法淘汰一页后调入所需的页，打印页表情况 。逐个地址访问，直到所有地址访问完毕 -topics : design a request page memory management program, and the simulation program specific requirements : 1. have a need to visit the directive addresses flow, without loss of generality. be appropriate (to use artificial methods specified or random number generator) to form the sequence, makes 50% of the order was the order of implementation. 25% of orders evenly spread address some of the former and 25% of the addresses are evenly spread in the latter part two addresses. The algorithm uses pages out pages out of FIFO algorithm, and eliminate one, the only page in the page table to erase. No longer judge whether it be redrafted, it was not to return to the three auxiliary depositors, have a need to visit the directive addresses flow; designate the appropriate size of the page (for exam
Platform: | Size: 3072 | Author: 周子藤 | Hits:

[VHDL-FPGA-Verilog] VHDL.fifo

Description: 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
Platform: | Size: 1178624 | Author: 黎莉 | Hits:

[Console] Memory.FIFO

Description: 操作系统中的 内存管理 FIFO算法模拟-OS FIFO memory management algorithm simulation
Platform: | Size: 1024 | Author: 静水 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows
Platform: | Size: 14336 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] Verilog_FIFO_ram

Description: 一个可以综合的Verilog 写的FIFO存储器，word格式-An integrated Verilog wrote FIFO memory, word format
Platform: | Size: 19456 | Author: hjx | Hits:

[OS Develop] FIFO

Description: 先进先出存储器的程序，希望对初学者有所帮助。-FIFO memory of the procedure, and they hope to be helpful to beginners.
Platform: | Size: 1024 | Author: tian | Hits:

[OS Develop] fifo

Description: 操作系统中内存页面的先进先出的替换算法fifo-Operating system memory page replacement algorithm FIFO fifo
Platform: | Size: 3072 | Author: gll | Hits:

[OS Develop] FIFO

Description: fifo.v verilog实现的先进先出存储器-fifo.vverilog realize the FIFO memory
Platform: | Size: 2048 | Author: patrick | Hits:

[OS Develop] fifo

Description: 利用一个SAM设计一个FIFO 的存储器-SAM uses a design of a FIFO memory
Platform: | Size: 9216 | Author: lzc | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: This code is a FIFO memory vhdl developed in ISE Software
Platform: | Size: 3377152 | Author: Arley | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: vhdl code for FIFO memory with controler
Platform: | Size: 730112 | Author: Mihai | Hits:

[VHDL-FPGA-Verilog] multiplier-ROM--FIFO-memory

Description: 布斯，阵列乘法器，加减交替除法器，以及ROM存储器，FIFO存储器-Booth, array multiplier, divider alternately add and subtract, and ROM memory, FIFO memory
Platform: | Size: 19456 | Author: ZY | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用verilog语言的实现FIFO存储器，以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)
Platform: | Size: 2048 | Author: ttian | Hits:
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